This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.

We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low power supply voltage operation below than 2.0 V. SPICE simulation has been carried out using 0.7 µm BiCMOS parameters and shows quite good transfer characteristics.

This paper describes a sub 1-V low noise amplifier (LNA) fabricated using a 0.35 µm SOI (silicon on insulator) CMOS process. The SOI devices have high speed performance even at low operating voltage (below 1 V) because of their smaller parasitic capacitance at source and drain than those of bulk MOSs. A body of a MOSFET can be controlled by using a field shield (FS) plate. The transistor body of the LNA is connected to its gate. The threshold voltage of the transistor becomes lower due to the body-biased effect so that a large drain current keeps the gain high, and active-body control improves the 1-dB gain compression point. A gain of 7.0 dB and a Noise Figure (NF) of 3.6 dB are obtained at 1.0 V and 1.9 GHz. The output power at the 1-dB gain compression point is +1.5 dBm. The gain and the output power at the 1-dB gain compression point are higher by 1.2 dB and 2.9 dB respectively than those of a conventionally body-fixed LNA. A 5.5 dB gain is also obtained at the supply voltage of 0.5 V.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

For the realization of low-voltage full-color FEDs, requirements for phosphor for the FED are proposed. Especially, the influence of released gases or substances from phosphors on the field emission within the FED was made clear. It was clarified that the analysis of F-N plots of the V-I curve of field emission characteristics was helpful to know the interaction of field emission and phosphors. In the experiment, we first obtained the depth from the phosphor surface of the low voltage electron excitation in case of ZnGa2O4, where the region available for cathodoluminescence at the anode voltage of 400 V is about 63 nm deep from the surface. The characteristic of the 12.4 cm-320(trio)240 pixels low-voltage full-color FED is reported. The luminance of 154 cd/m2 was attained at the anode voltage of 400 V and the duty factor of 1/241. Supported by the high potential of the FED as a flat panel, each problem shall be steadily solved to secure the firm stand as a new full color flat display in new applications.

In this work, a CMOS on-chip current reference circuit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is nearly insensitive to temperature and supply-voltage variations. In the proposed circuit, the current component with a positive temperature coefficient cancels that with a negative temperature coefficient each other. While conventional current reference circuits are based on bipolar transistors in BiCMOS, bipolar, or CMOS processes, the proposed circuit can be integrated on a single chip with other digital and analog circuits using a standard CMOS process and extra masks are not required. Measured results are demonstrated for two different prototypes. The first is fabricated employing a 1.0 µm p-well double-poly double-metal CMOS process and operates at 5 V nominally. The second, based on a 0.6 µm n-well process, is optimized for 3 V to 5 V operation. The latter prototype achieves the temperature coefficient of 98 ppm/ over a temperature range from -25 to 75 and the output variation of 1.5% with the supply-voltage changes from 2.5 V to 5.5 V. A simple calibration technique for reducing output current variations improves circuit yield.

This paper describes an MOS current-mode, voltage-controlled oscillator (VCO) circuit that potentially operates with a 2 V supply voltage, 500 MHz oscillation frequency, and -90 dBc/Hz phase noise at the 1 MHz offset. It also has an improved oscillation frequency linearity of the control voltage and 11 mW power dissipation. The oscillation frequency reached 920 MHz when the supply voltage was increased to 3 V.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.